This post has been sitting in my draft folder for a very long time, I forgot about it, but here it is –
Third round of job searching. I didn’t get nearly as many interviews as I had hoped, probably due to sloppy resume, and I’m also a lot more selective this time, applying only to hardware positions (too much software for me, need to take a break… life is about balance!). I did get some really cool interviews, though.
nVidia (System Engineer, post-silicon verification)
Very intense interview! An entire hour of quizzing, on everything from C++ to analog circuits (filter transfer function). Most of them are fairly standard, though, and programming part is easy (I guess they don’t really expect electrical engineers to know how to program). I can’t believe I actually programmed in C++ and VHDL over the phone.
- How to construct a NOR gate using 1 input multiplexers? (LUT, cascaded muxes)
- How to construct a D flip flop with async reset from regular DFF (I’m still not sure. Mux on output and input?)
- Merge 2 files containing lists of words, remove duplicates, sort, and output to third file (binary search tree, pre-order traversal)
- Given a series RC circuit, determine response at DC and 1MHz (1 pole transfer function)
- 100 students took an exam. mean score = 500, SD = 100. Highest 15% pass. Is 650 pass? (basic stats)
- With a 3L cup, a 5L cup, and infinite supply of water, measure 4L (classical interview question. somewhat hard. did a depth-first search in my head)
nVidia second interview
This one is all on digital logic, still fairly difficult. Talked in detail about the PCB I made for robotics lab, and firmware programming.
- How to construct a D-latch using transmission gates and inverters (digital feedback, bus contention)
- What is the delay of the latch (add up delays of signal path)
- How to construct a D-flipflop using 2 D-latches (in series, one gets inverted clock)
- What are the parameters (setup time, clock-to-Q) of the D-FF (delay of first latch, and delay of second latch)
- 2 D-FF with combinational logic between them. What is the timing constraint given delay of the logic circuit, setup time, clock-to-Q, clock delay to second FF, and clock jitter (clock jitter is the hard part, 2tj must be added because in worst case, 2 clock edges can be T/2 + 2tj apart)
Nuvation (firmware developer)
Mostly talked about projects I have done.
- on a microcontroller, when is it appropriate to use interrupts, when is it not? (responsiveness, external stimuli, easy to introduce bugs if interrupt handler shares data with main loop, etc)
- how to test software (whitebox, blackbox, edge cases, typical cases, etc, big words, pretend to be a software engineer)
Nuvation second interview
Again mostly projects I have done, and some project management stuff. How I organize the electrical team at Thunderbots, etc.
- how to implement brushless motor controller in FPGA and MCU (probably because I mentioned brushless motors in my resume)
- some simple questions about PCB design that I don’t remember. Something about vias and component packages…
Sifteo (Electrical engineer)
Mostly talked about my involvement with Thunderbots, and PCB design experiences, and what is it like to work at Sifteo. They make very cool stuff!
- how to bring up and test a new circuit (different approaches, top-down, bottom-up, etc)
I really liked the Sifteo position, but I ended up choosing NVIDIA because it’s my first work term in the US, and working for a big company simplifies things (visa, housing, etc). And California!!!