For some reason, I really hate talking on the phone.

Talking face to face is the best, e-mail is ok, IM is good, I don’t mind texting, Facebook flirting is cute, snailmail is… snail? body language? be my guest. Feet tangling under the table? I’ll let you know when I get a gf.

But I just hate talking on the phone, and I don’t know why.

At first I thought it’s because the real time nature of talking on the phone (compared to IM or e-mail) doesn’t allow me to rethink what I’m about to say. Which makes sense, except I love talking IRL, which also has the same problem (saying things I wouldn’t have said if I thought about it for 0.5 more seconds).

Now I think it’s because IRL, I get to observe the other person, but not on the phone. I tend to do that a lot. For me talking on the phone feels like talking into a uni-directional pipe. There’s minimal feedback, which brings fear of misunderstanding, especially since I like to say things in super concise ways. And I also don’t get to pace the conversation with body language, which would just be awkward silences on the phone, and that freaks me out. It also seems like silences IRL is fine, but not on the phone, because both people need to sustain effort to hold the phone, and that would be a little silly if no one is saying anything.

Short informational calls are fine, but I don’t like “real” conversations over the phone. Talk to me IRL! (except for urgent matter, like I totally forgot there’s an ECE 353 lab or something… has that ever happened?! =P)

2-layer PCB routing for FPGA

(If you are not an electrical engineer, this post probably won’t be terribly interesting to you. Sorry about that. I really should start separate blogs for my hundred different faces)

Have you tried using an FPGA in your design? If you haven’t, you should! They are seriously awesome beasts.

They are also surprisingly easy to use, electrically, requiring no more than about a dozen connections for programming/configuration, and is perfectly doable for hobbyists (or at least hobbyist engineers), if you just spend a few hours reading a datasheet.

One big headache, though, is how to route the power supply. Most modern FPGAs require 3 power nets – Vccint (supply for internal core logic), Vccaux (axillary supply for PLL, configuration logic, etc), and Vccio (supply for I/O buffers). On a typical hand-soldering-friendly TQFP FPGA, you would have a few power pins on each side, for ALL 3 supplies! That’s a lot of trouble for routing. How do you connect all those pins on a 2 layer board?

To make things even more interesting, there’s decoupling to worry about. Decoupling is very crucial for FPGAs because they switch fast, and like to draw current in huge spikes, and if you have a long power trace powering the FPGA from a distant regulator, that’s bad news, because traces have some resistance and inductance. That means, voltage will dip on the FPGA end, and it won’t operate reliably. The way to solve it is to have low ESR and ESL capacitances near power pins, which, of course, is easier said than done.

That’s the theory. How do we do it in practice?

For slower and lower power chips, the standard solution is to add capacitors very close to power pins, to ground. That way, all power pins will have “little reservoirs” to supply little spikes and prevent voltages from dipping. If you are extra careful (or for sensitive chips), you can even have a few capacitors in parallel to decouple different frequencies. Something like 4*0.01uF//2*1uF//10uF is pretty common. It all depends on how the chip draws current.

FPGAs and high speed microprocessors are the worst kind. They don’t draw any current most of the time, but they do it in huge spikes, at the operating frequency. For an FPGA, the spikes can easily be a few amps.

Also, at very high frequencies (>100MHz), capacitors aren’t enough. They won’t do much because the ESR/ESL will stop them from supplying big spikes of current, and the voltage will still dip. We need something called plane capacitors, which are the capacitances formed by 2 big polygons on 2 layers of a PCB, separated by the PCB dielectric (usually fiberglass). I can’t find it anymore, but I once read a paper that says, at frequencies lower than 100MHz, the capacitors will supply most of the current, and at frequencies higher than 150MHz, the current will be almost entirely handled by the plane capacitors.

That’s the theory. How do we do it?

Xilinx recommends 4 layer board minimum, with 3 power planes for the 3 voltages, and 4th one for ground. That’s good, except 4 layer boards cost about twice as much as 2 layer boards (~$300 instead of $150 for a 5″ by 5″ board), and if the design doesn’t otherwise need a 4 layer board, that’s a waste. They also recommend connecting all power pins (so all parts of the chip has low impedance paths to power), and decoupling all power pins.

I have been thinking about how to do it on 2 layers for a few weeks, and I think I came up with a very good way, that is very clean and follows Xilinx’s recommendation fairly closely.

This only works with FPGAs where Vccaux and Vccio can be the same, because I’m cheating a bit by using only 2 different voltages.

Vccint has to be 1.2V on both Xilinx and Altera FPGAs, so nothing we can do here.

Vccio has to be the I/O voltage of your design (up to 3.3V), so it’s usually 3.3V.

Vccaux, though, is where the fun is. On older FPGAs, it has to be 2.5V, which is pain in the rear end. There’s only one series I know that allow 3.3V on Vccaux are the Spartan-3A and Spartan-3AN, so I recommend using them. On Altera Cyclone III and older Xilinx Spartan’s, Vccaux has to be 2.5V. So no love for Altera!

It looks like this –


Basically, underneath the FPGA, instead of having a ground plane, I have 1.2V on the top layer, and 3.3V on the bottom layer. Then, all the 1.2V pins can be connected with short traces, and 3.3V through a via and 2 short traces (slightly worse than just a short trace). I gave 1.2V more love because FPGA draws most of its power from there (bigger FPGAs can draw a few amps on the 1.2V rail), and an unstable Vccint can cause device malfunction. 3.3V is only used to drive slower stuff (I/O buffers mostly), and won’t cause system failure.

And then, all the power pins are decoupled with capacitors as shown.

In this routing scheme, the 2 power planes decouple each other, which is not as nice as having them both decouple to ground, but it should still be pretty good. And every power pin can have short traces to capacitors. This routing scheme also doesn’t clutter the area around the FPGA, and wreck havoc with all the I/O signals coming in. I think it’s pretty nice.

My first PCB using this routing method has just been sent to manufacturing. Will see what happens! It’s the main board for my quadrocopter project, which I hope to write about in a bit. A rough log is here –

Hope this helps someone someday! (Hello Googler!)