Introducing… *suspense* the iScope!
No, just kidding. I hate Apple with a passion, due to the things they’ve done recently. But that’s for another time =P.
I’ve been working on it for a few weeks. The schematics is all done, so I thought I would document it a bit.
Goals (where they came from will become clear later) –
100 million samples per second (Msps), 40MHz bandwidth
2 channels at full speed
USB interface (USB powered)
Compatible with regular 1x and 10x BNC oscilloscope probes (direct connection and 10:1 attenuation)
– meaning input characteristics of 1MΩ in parallel with ~20pF (to make sure the probe can compensate for it)
True range selection (apparently some cheap USB scopes don’t have this)
Flexible triggering (including pre-trigger data view)
Offset (true differential)
Protected (diode clamped) inputs
Nice to have –
Cheap (-er than ridiculously priced low end USB scopes at least)
Calibration output (1kHz square wave)
Internal attenuation to allow big input
Major design decisions –
How does the data get from ADC to computer?
Streaming over USB is not an option. USB (even 2.0) is too slow. Even if we can somehow run it at the theoretical maximum speed of 480Mbps (or 60MB/s), at 8-bits per sample, that’s only good for 60Msps. 40Msps more realistically. We need 2x100Msps.
So there has to be an onboard buffer.
Then there’s the choice of microcontroller vs CPLD vs FPGA.
Microcontrollers are too slow. It would take about 10 clocks minimum to get one sample from the ADCs (toggle ADC clock, read input, check overflow, check triggering, etc). Meaning we’ll need a microcontroller/processor that runs at about 1GHz. A Core 2 Duo in an oscilloscope, anyone?
Programmable logic (CPLDs and FPGAs) is a more sensible choice because they can do many things in parallel.
CPLDs are cheap, easy to wire up, and hand soldering-friendly, but they require a bunch of supporting chips – a microcontroller, SRAM chip, and PLL chip (or very high speed oscillators, which are bloody expensive).
An FPGA, on the other hand, can synthesize the microcontroller, memory (RAM blocks), and has internal clock manager (PLL).
I ultimately decided to go with the FPGA, since they are cheaper (if you count all the external chips saved), and bigger in case I decide to add other things later on.
It was a choice between Xilinx Spartan-3AN and Altera Cyclone. I like the Altera development software more… but the Xilinx chip is much more impressive. It has built-in flash memory (non-volatile, and no need for an external ROM), and is a little cheaper. So I went with Spartan-3AN (XC3S50AN in TQFP-144 package).
It’s easier to wire up than I thought. Just 2 voltage rails (3.3V and 1.2V), clock, and JTAG for programming. The rest are all I/O pins.
The USB interface chip is FT245 (USB to FIFO) instead of the more common FT232 (USB to UART) because I am too lazy to make a UART in VHDL =P. Drawing 6 more wires (parallel interface) is easier.
ADCs are a pair of AD9283 from Analog Devices. 100Msps, buffered input, parallel output, simple interface. What more can you ask for?
DAC chosen is AD5724. Quad bipolar output (output can go negative), 12-bit, SPI. Bipolar output is hard to find, but that saves 2 op amps to do level shifting. The DAC is used to generate offset voltages.
Now the interesting part – analog front end!
Input goes into a 1MΩ metal film resistor in parallel with 20pF ceramic cap (not sure about this). Buffered by a Texas Instruments OPA656 wideband op amp with JFET input (very high impedance, which we need, because the probe has high input impedance. Downside? bloody expensive).
The next stage is a Texas Instruments THS7002 dual programmable gain amplifier. Each channel consists of a pre-amplifier (regular high speed op amp) and a second amplifier with a gain selected by a 3-bit digital input.
I use the pre-amps as good old op amp summers to add offset to the signal.
The amplifiers have 70MHz bandwidth, way higher than what we need. Interestingly, that doesn’t depend on gain. Usually, voltage feedback amplifiers have a fixed gain-bandwidth product (GBW), so for example, the bandwidth at gain = 2 will be approx. half of the bandwidth at gain = 1. Not for this one. Cool stuff.
Power supplies –
5V is provided by USB. -5V is 5V doubled and inverted (by the LM2682 charge pump), then regulated down (up) to -5V. 3.3V and 1.2V are from linear regulators (MCP1825S-33 and MCP1825S-12). The FPGA can potentially consume a lot of current on the 1.2V line, so making it a switching regulator can make it a lot more efficient. I don’t think it’s necessary, though, and I don’t really want to deal with inductors (and their EMI noise).
Clock for the FPGA is from a 25MHz oscillator. Will be pumped up to 200MHz (x8) by the FPGA’s phase locked loop. Hopefully.
Any suggestions? 🙂
Bill of Material –
|XC3S50AN Spartan 3AN FPGA, TQFP-144, Speed Grade 5
|THS7002 Programmable Amplifier, 70MHz
|OPA656 500MHz Op Amp with JFET Input
|AD9283 8-bit parallel ADC, 100Msps version
|AD5724 12-bit SPI Bi-polar DAC
|MCP1825S-33 3.3V Low-Dropout regulator
|MCP1825S-12 1.2V Low-Dropout regulator
|MC7905 -5V regulator
|LM2682 Doubling Inverter (Charge Pump)
|FT245RL USB to FIFO Interface chip
|USB mini-b connector
Adds up to $107.58. All prices from Digikey, at single quantities.
However, if you are a university student, you can get most of the expensive chips for free from the manufacturers as samples. Most of them don’t mind giving samples to students. Don’t lie, that’s bad. Just ask nicely.
I got the amplifiers, the ADCs, and the DAC for free.
Even if you are paying for everything, you should be able to have the whole thing built for about $150 (passive components, and PCB). Cheaper than all comparable commercial scopes I could find.
If you are using free chips, aim for $50?
I haven’t started on the software yet, but it will most likely be open source (just like all the rest of the design) and cross-platform, using Qt.
I’m most worried about the hardware, since I know a little programming :).
Knowing myself, there are probably tons of mistakes/oversights in the circuitry. Help?